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NXP Semiconductors /LPC43xx /UART1 /IER

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Interpret as IER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLE)RBRIE 0 (DISABLE)THREIE 0 (DISABLE)RXIE 0 (DISABLE)MSIE 0RESERVED 0 (DISABLE)CTSIE 0 (DISABLE)ABEOIE 0 (DISABLE)ABTOIE 0RESERVED

RXIE=DISABLE, ABEOIE=DISABLE, ABTOIE=DISABLE, CTSIE=DISABLE, RBRIE=DISABLE, MSIE=DISABLE, THREIE=DISABLE

Description

Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0)

Fields

RBRIE

RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.

0 (DISABLE): Disable. Disable the RDA interrupts.

1 (ENABLE): Enable. Enable the RDA interrupts.
THREIE

THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].

0 (DISABLE): Disable. Disable the THRE interrupts.

1 (ENABLE): Enable. Enable the THRE interrupts.
RXIE

RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].

0 (DISABLE): Disable. Disable the RX line status interrupts.

1 (ENABLE): Enable. Enable the RX line status interrupts.
MSIE

Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].

0 (DISABLE): Disable. Disable the modem interrupt.

1 (ENABLE): Enable. Enable the modem interrupt.
RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
CTSIE

CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.

0 (DISABLE): Disable. Disable the CTS interrupt.

1 (ENABLE): Enable. Enable the CTS interrupt.
ABEOIE

Enables the end of auto-baud interrupt.

0 (DISABLE): Disable. Disable end of auto-baud Interrupt.

1 (ENABLE): Enable. Enable end of auto-baud Interrupt.
ABTOIE

Enables the auto-baud time-out interrupt.

0 (DISABLE): Disable. Disable auto-baud time-out Interrupt.

1 (ENABLE): Enable. Enable auto-baud time-out Interrupt.
RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data